Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design /

Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design /

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Detaylı Bibliyografya
Kurumsal yazarlar: IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design Houthalen, Belgium, Interuniversity Micro-Electronics Center
Diğer Yazarlar: Claesen, Luc J. M.
Materyal Türü: Konferans Sunumu Kitap
Dil:English
Baskı/Yayın Bilgisi: Amsterdam ; New York : New York, N.Y. : North-Holland ; Distributed in the U.S. and Canada, Elsevier Science Pub. Co., 1990.
Seri Bilgileri:VLSI design methods ; 2
Konular:
Integrated circuits > Very large scale integration > Design and construction > Data processing > Congresses.
Computer-aided design > Congresses.
Integrated circuits > Verification > Congresses.
Diğer Bilgiler
Fiziksel Özellikler:xv, 427 p. : ill. ; 23 cm.
Bibliyografya:Includes bibliographical references.
ISBN:0444886885 (U.S.)

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