Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design /

Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design /

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Dettagli Bibliografici
Enti autori: IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design Houthalen, Belgium, Interuniversity Micro-Electronics Center
Altri autori: Claesen, Luc J. M.
Natura: Atti del Convegno Libro
Lingua:English
Pubblicazione: Amsterdam ; New York : New York, N.Y. : North-Holland ; Distributed in the U.S. and Canada, Elsevier Science Pub. Co., 1990.
Serie:VLSI design methods ; 2
Soggetti:
Integrated circuits > Very large scale integration > Design and construction > Data processing > Congresses.
Computer-aided design > Congresses.
Integrated circuits > Verification > Congresses.
Descrizione
Descrizione fisica:xv, 427 p. : ill. ; 23 cm.
Bibliografia:Includes bibliographical references.
ISBN:0444886885 (U.S.)

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