LEADER 01859nam a2200421 a 4500
001 c000183144
003 CARM
005 20031001222217.0
008 840713s1984 maua b 001 0 eng
010 |a 84015490 //r85 
019 1 |a 3315533  |z 23968294  |5 LACONCORD2021 
020 |a 0898381649 
035 |a (OCoLC)10998529  |5 LACONCORD2021 
040 |a LC  |b eng  |c LC  |d NU 
050 0 0 |a TK7868.L6  |b L626 1984 
050 1 4 |a TK7868.L6  |b L626 1984 
050 4 |a TK7868.L6  |b L63 1984 
082 0 4 |a 621.381/73  |2 19 
082 0 4 |a 621.381/73  |2 20 
082 0 4 |a 621.381/73 
245 0 0 |a Logic minimization algorithms for VLSI synthesis /  |c by Robert K. Brayton ... [et al.]. 
246 3 |a Logic minimization algorithms for V.L.S.I. synthesis. 
260 |a Boston :  |b Kluwer Academic Publishers,  |c c1984. 
300 |a ix, 193 p. :  |b ill. ;  |c 25 cm. 
490 1 |a The Kluwer international series in engineering and computer science ;  |v SECS 2.  |a VLSI, computer architecture, and digital signal processing. 
500 |a Includes index. 
504 |a Bibliography: p. [174]-190. 
650 0 |a Logic design. 
650 0 |a Integrated circuits  |x Very large scale integration. 
650 0 |a Integrated circuits  |x Design and construction  |x Data processing. 
650 0 |a Algorithms. 
700 1 |a Brayton, Robert K.  |q (Robert King) 
740 0 |a Logic minimization algorithms for V.L.S.I. synthesis. 
830 0 |a Kluwer international series in engineering and computer science.  |p VLSI, computer architecture, and digital signal processing. 
830 0 |a Kluwer international series in engineering and computer science ;  |v SECS 2. 
852 8 |b CARM  |h A2:AK26C0  |i C06406  |p 0243338  |f BK 
999 f f |i ae92775c-9c8c-53fb-b26e-874a7f079a2c  |s 42d66556-59a0-58d8-9205-8289f1f721d1 
952 f f |p Can circulate  |a CAVAL  |b CAVAL  |c CAVAL  |d CARM 1 Store  |e C06406  |f A2:AK26C0  |h Other scheme  |i book  |m 0243338