Evaluating a chip, wafer, or lot using SUXES, SPICE, and STAT2 /

Evaluating a chip, wafer, or lot using SUXES, SPICE, and STAT2 /

Enregistré dans:
Détails bibliographiques
Auteur principal: Marshall, J. C. (Janet C.)
Collectivité auteur: National Institute of Standards and Technology (U.S.)
Autres auteurs: Mattis, Richard L.
Format: Livre
Langue:English
Publié: Gaithersburg, MD : Washington, DC : U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology ; For sale by the Supt. of Docs., U.S. G.P.O., 1992.
Collection:Semiconductor measurement technology
NIST special publication ; 400-90
Sujets:
SPICE (Computer file)
Metal oxide semiconductors, Complementary > Computer simulation.
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035 |a (OCoLC)26530605  |5 LACONCORD2021 
040 |a LC  |b eng  |c LC  |d LC 
050 0 0 |a QC100  |b .U57 no. 400-90  |a TK7871.99.M44 
082 0 0 |a 621.3815/2/0287  |2 20 
100 1 |a Marshall, J. C.  |q (Janet C.) 
245 1 0 |a Evaluating a chip, wafer, or lot using SUXES, SPICE, and STAT2 /  |c J.C. Marshall and R.L. Mattis. 
260 |a Gaithersburg, MD :  |b U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology ;  |a Washington, DC :  |b For sale by the Supt. of Docs., U.S. G.P.O.,  |c 1992. 
300 |a iv, 140 p. :  |b ill. ;  |c 28 cm. 
490 1 |a Semiconductor measurement technology 
490 1 |a NIST special publication ;  |v 400-90 
500 |a "April 1992." 
504 |a Includes bibliographical references (p. 41-42) 
650 0 |a Metal oxide semiconductors, Complementary  |x Computer simulation. 
630 0 0 |a SPICE (Computer file) 
700 1 |a Mattis, Richard L. 
710 2 |a National Institute of Standards and Technology (U.S.) 
830 0 |a Semiconductor measurement technology 
830 0 |a NIST special publication ;  |v 400-90 
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